Design of High-Fold Encoders

• Main Authors: Yong-Quan Lin, 林勇全
• Other Authors: Ming-Shyan Wang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/73240211942328558103

碩士 === 南台科技大學 === 電機工程系 === 94 === A high-performance motion system must rely on a high-resolution encoder to offer the speed and position signals, close the control loops, and show its excellent performance. However, the cost of an encoder is about half that of a motor rated below 1 hp. In order to reduce cost and raise the resolution, it is necessary to explore its internal circuit. In the thesis, the relationship between sine and cosine functions is considered to obtain a four-fold frequency of the original by interpolating, and to utilize the phase-lag approach to raise it two times. In addition, the detection of rising and falling edges of channel A and channel B of an encoder is utilized to get the other four times in frequency. The algorithm to raise 32-fold times in frequency is implemented by two ways, hardware circuit or microcontroller-based circuit, in the thesis. Additionally, design on absolute encoders by sputtering thin film onto the disk is also studied. There generally exist variations of amplitude, phase, and DC level for the sinusoidal waveforms detected from the encoder. The thesis will discuss these issues and the compensation methods to get smooth waveforms by using FPGA/CPLD, ADC, and DAC. Finally, the algorithms and circuits will be applied to an optical encoder and a magnetic encoder to demonstrate their effectiveness.