| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 94 === With lossless compression, the raw or original source data is recovered exactly after decompression is employed as a means to bring significant advantages to computing systems. In recent years, due to the combination of pressure for more bandwidth allied and the need to improve storage capacity, the successful applications of lossless data compression have been increasing in the fields of storage systems, data transmission systems and communication networks. However, in systems that operate at a data rate of over Gbits per second, the data compression is not used to its full benefits subjected to performance limitations encountered in the data compression hardware.
A modified algorithm for high-speed lossless data compression is presented in this paper. Our algorithm improves the data compression ratio in two ways: By using the property of recurrence, the Run-Length-Internal (RLI) full match has been moved one match ahead; in the mean time, by re-ordering the coding stream, the bit-length that uses to represent the RLI has been reduced. Further, the proposed hardware implementation with low complexity, low cost and 2.1 Gbits/s high data throughputs has been correctly verified via the Altera APEX20KE EP20K200EFC484-1 FPGA technology.
The simulation result shows that the clock rate of the proposed high-speed lossless compressor can work at the speed of 66.9MHz and the compression ratio is ((Input-Output)/Input) approximated to 41.2%. Therefore, we can see that the design and implementation of the proposed lossless compressor can effectively achieve better data compression throughputs and compression ratio in a system operating at a Gbits bandwidth.
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