Analog CMOS integrated circuit implementation of the photonic lock-in amplifier

• Main Authors: Zheng-Shuo Tong, 童政碩
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/4w3d2c

碩士 === 國立虎尾科技大學 === 光電與材料科技研究所 === 94 === In this thesis, we propose the analog CMOS integrated circuit implement of a Lock-in amplifier. This design is based on a two-stage operational amplifier (OPA). A dual-output OP amplifier, a four-quadrant analog multiplier, a square-root circuit, a modulus circuit, and a division circuit are all based on this OPA. The design parameters are based on the TSMC 0.35 μm process. The OPA has an open-loop gain of 80 dB and the multiplier has a linear output range of ± 0.4 V. The key technique applied in Lock-in amplifier is the Phase-Sensitive Detection (PSD), which pick the signal with the specific frequency and phase by multiply the input signal with a reference signal. The result signal is then filtered by a low pass filter to obtain a DC value. Finally, the output voltage value is normalized to overcome the light intensity variation problem. The test input signal voltage is about 1 μV~50 μV and the bandwidth is about 50 Hz~1 kHz. A photo detector is also fabricated on the identical chip .The total power consumption is about 66 mW.