| Summary: | 碩士 === 國立高雄大學 === 電機工程學系碩士班 === 94 === In this thesis, we have explored and discussed about designing FIR digital filter, and indeed we have accomplished IC circuit task. According to this theory designing, we are trying to use the method of Least Squares Approach in order to design the optimized filter which is involved 1D & 2D. In addition, we also are using the method of Lagrange Multiplier Approach in order to design the FIR digital filter that extra function might add optional limited conditions. Furthermore we tried to use the later, designed a coefficient which is a finite bit filter. On the above filter performing, we are using both constructions. One adopt the Construction of Multiplier, and another is performed the Construction of Multiplier with a shift register. Meanwhile for the adder performing, we are wholly using the framework of Carry Save Adder. On the one hand, we also have accomplished the filter bank designing that involved a organized encoder and decoder. Hence, concerning the above circuit designing, all can be proved with Verilog hardware stated language and FPGA, and according to the presented of experimental result, concluded that it is possible to whole relative designing.
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