A Layout Study of Light Emission and Light Detection Devices Using CMOS

• Main Authors: Yi-fu Chen, 陳奕甫
• Other Authors: C. K. Liu
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/85szgg

碩士 === 國立臺灣科技大學 === 電子工程系 === 94 === In this thesis, a layout study of light emission and light detection devices using CMOS is presented. CMOS process provided by CIC (Chip Implement Center) is used. Here, we study four topics: the silicon light emission, the silicon photodiode, the transimpedance amplifier and the photogate receiver. The first part deals with the CMOS silicon light-emitting device. We use four types of devices to compare the characteristics of silicon light emitting devices. Four silicon light emission devices, of pn junctions are designed. The quantum external efficiencies are 2.12×10-6, 3.00×10-6, 3.02×10-6 and 3.6×10-6, with an area of 90 × 244 μm2, 110 × 263 μm2, 220 × 230 μm2 and 200 × 300 μm2, respectively. The second part is about the silicon photodiode. A maximum responsivity R=1.54×10-3(A/W) and a quantum efficiency =0.091 are obtained. The third part is about the transimpedance amplifier employing current mirrors. Our simulation results can reach 74dBΩ gain and 735MHz bandwidth. In the last, the fabrication of optical receiving circuit of the photogate type is described. It can store the charges generated by light illumination in the potential well temporarily. It can also transfer the electric charges to distinguish the signal from the background light. In the topics mentioned above, they have the same feature in the use of material, and it can be applied to realize the opto-electronic interconnect among integrated circuit chips.