Switched-capacitor second-order Sigma-Delta modulator

• Main Authors: Yan-chen chen, 鄭彥誠
• Other Authors: Poki Chen
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/qakd3s

碩士 === 國立臺灣科技大學 === 電子工程系 === 94 === Oversampling techniques based on delta-sigma modulation are widely used to implement the interface between analog and digital signals in VLSI systems, such as digital audio systems. This type of systems requires a large dynamic range (i.e., about 16 ~ 20 bits) at low-frequency bandwidth of 20 kHz. The delta-sigma modulation approach is relatively insensitive to imperfections in circuit components and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. In particular, oversampling architectures is a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison Nyquist-rate converters. Furthermore, they allow the performance requirements, and thus most of the power dissipation, to be concentrated in the input stage of a converter. For a multibit ΔΣ modulator, the performance is directly related to the linearity of the internal multibit DAC in the feedback path. Various dynamic element-matching techniques have been proposed to circumvent the nonlinearity of the internal DAC. By using these techniques, the DAC noise is also shaped like quantization noise in delta-sigma modulators. This thesis describes the results of research into the design of the oversampling one-level delta-sigma modulators implemented by switch-capacitor circuits, digital audio applications. The experimental modulators described herein can deliver a high dynamic range over a 20 kHz bandwidth and have been fabricated in standard 0.35 μm CMOS technologies.