Synthesis of Low Power PB-CAM

• Main Authors: Chun-Chih Chen, 陳俊致
• Other Authors: Shanq-Jang Ruan
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/cddttp

碩士 === 國立臺灣科技大學 === 電子工程系 === 94 === Content addressable memory (CAM) is a major device in asynchronous transfer mode (ATM), communication networks, LAN bridges/switches , databases, lookup table , and tag directories in fully associative cache systems, due to its high-speed parallel data searching operation. Hence, the operation of CAM requires an enormous number of comparison operations. Obviously, these comparison operations consumes a large amount of power. In this paper, we propose a Gate-Block-Selection algorithm to construct a low power PB-CAM to reduce the comparison operation number. By our theoretical analysis, we can reduce 19.0 % at least, 26.6 % at most. the total number of the comparison operation of our Gate-Block-Selection algorithm is much less than that of the Block-XOR approach. Moreover, we implemented both the Block-XOR PBCAM and our Gate-Block-Selection PB-CAM in the TSMC 0.18-μm digital CMOS process technology and measure the power consumption by Nanosim. Compared to Block-XOR approach, the experimental result shows that our Gate-Block-Selection PB-CAM comsumes 3.1% at least and 13.3% at most less power than Block-XOR does. The major contribution of our paper is that we provided theoretical and practical proof to verify that our gate-block-selection approach can further reduce the power consumption to fit different benchmark. Therefore, our Gate-Block-Selection PBCAM is very suitable for embedded systems.