| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 94 === In this master thesis, a low-power and high-quality preserving DCT architecture is presented. It is obtained by optimizing the Loeffler DCT based on the Cordic algorithm. The computational complexity is reduced significantly from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (i.e., similar to
the complexity of the binDCT) without sacri‾cing the transformation accuracy. This implementation can also perform multiplierless DCT transformation as binDCT does.
In our experiments, we used different criteria to evaluate the proposed DCT architecture. After synthesizing with TSMC 0.13-um technology library, Synopsys PrimePower was used to estimate the power consumption at gate-level. Then we have embedded our DCT architecture into the JPEG and XVID CODECs to compare and analyze the quality of the compression results. The experimental results show that the proposed DCT architecture only occupies 19% of the area and consumes about 16% of the power of the Loe²er DCT. Moreover, it also retains the good transformation quality of the original Loeffler DCT.
As a result, the proposed Cordic based Loeffler DCT is not only very suitable for low-power and high-quality CODECs but also highly suited for VLSI-implementations since it only needs add and shift operations to carry out DCT transformation. Finally, it is worth noticing that the presented Cordic based Loeffler DCT architecture is especially suited for embedded systems, high-quality CODECs and mobile hand-held
devices due to its low power and small area properties.
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