| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === In a Critical-Mode Power Factor Correction circuit, the switching frequency is variable. The frequency can be considerably higher when the input voltage waveform is near the valley point. This leads to higher switching loss during this period of time. Since the contribution to power factor correction and output power throughput during this period is insignificant but MOSFET switching loses are high, it’s better just to cut off the MOSFET switch during this period. In other words, one can set a frequency limit beyond which MOSFET is cut off. This is called Truncated CRM operation in this thesis. This method saves power especially when the circuit is under stand-by mode. There is a mandate to reduce this type of loss because in many house-hold applications the equipment are most of the time at stand-by mode.
In the thesis, an analysis was conducted to find out how the various PFC performances such as power factor, harmonic current, and conduction angles depend on circuit parameter and working conditions. These relationships were also used to help design the Truncated-CRM PFC circuit in the thesis.
Two CRM PFC circuits are often interleaved to provide higher output power. Because of interleaving, the ripple current of the capacitors can be reduced. An analysis was also conducted to find out the ripple information in terms of circuit parameters and operating conditions. This information is also useful to the designers.
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