A Programmable Gain Amplifier with Integrated RSSI Function for Wireless Communication Systems

• Main Authors: Chun-Pang Wu, 吳駿邦
• Other Authors: Hen-Wai Tsao
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/55053336258776684602

博士 === 國立臺灣大學 === 電機工程學研究所 === 94 === In this thesis, a CMOS intermediate frequency (IF) programmable gain amplifier (PGA) for superheterodyne and digital-IF systems is proposed. This amplifier could be operated under two different power modes. It maintains a 3dB bandwidth greater than 110MHz under normal power mode and 71MHz under low power mode. And it could provide a power gain control range from -7.78dB to 79.79dB in normal power mode (at 110MHz) and -7.79dB to 80.03dB in low power mode (at 71MHz) with 1dB step resolution and the gain error is within ±0.4dB for both modes. Integrated with this PGA is a CMOS logarithmic successive detecting amplifier with a ±0.7dB logarithmic accuracy for the input signal ranging from -83dBm to -3dBm. The proposed PGA is fabricated in a 0.35μm 1P4M CMOS process. The capacitors used for frequency compensation in the operational amplifier for the bias circuit of the fixed gain stages are realized with MOS capacitors. The gain programming logic circuit and RSSI circuit are also integrated with the proposed PGA. The measured output 1dB compression point is -4dBV, and the third order output intercept point is 10.6dBV. The whole circuit consumes 13mA current when operated in normal power mode and 5mA current when operated in low power mode from a 3V power supply. The chip area, including pads, occupies 1.5×1.5mm2.