Flip-chip transition measurement and design of performance improved inductors and higher process tolerance coupled mutual inductors in multilayer structure

• Main Authors: Tzu-Wei Chao, 趙子威
• Other Authors: Hsin-Chia Lu
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/37660440575992865804

碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === There are three topics in this thesis. The first topic is the flip-chip transition measurement up to millimeter wave frequency. The second is the design of performance improved inductors in the LTCC substrate. The last is the capacitor and coupled inductor with high process tolerance in the multilayer structure. The characteristics of the conventional flip-chip are studied and obtained by the simulation. Its narrowband and wideband improvements are simulated and presented. Then we propose two measurement methods to extract the property of the flip-chip up to millimeter wave frequency. One is back-to-back flip-chip measurement method and the other is PRM (port reduction method). The programmable termination in CMOS circuit is designed and simulated for PRM. To optimize the inductor design, the influence of the geometry on the inductor’s performance are introduced and analyzed. Then the spiral, multilayer, helical and solenoid inductors are designed and its performance on inductance, quality factor and self resonant frequency are compared. The spiral inductors with patterned or hollow ground are analyzed and designed to improve its performance. Finally, the center tapped inductors are designed for differential circuit with better symmetry property. All of inductors are designed in the LTCC substrate. The capacitor and coupled inductor with high process tolerance are proposed to withstand the misalignment between stacked layers due to process variation. The transmission zero circuit and bandpass filter implemented with these components are designed and simulated to test the performance of high process tolerance in the circuit level.