| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === Multi-phase clocks generators are useful in many applications. In high-speed serial link applications, multi-phase clocks are used to process data streams at a bit rate higher than internal clock frequencies. In wireless LAN baseband design, the multiphase clocks can be used to find a better sampling point for the ADC to improve overall system performance. Here, we use a DLL-based clock generator with nonoverlapping circuit to generate three nonoverlapping phases used for capacitor error-averaging in pipelined ADC.
Improvements in technologies and design make it possible to use successive approximation ADCs for video applications, where sample frequencies of at least 10MSample/s are necessary. The advantages by changing the structure of the ADC from subranging or pipelined to successive approximation are decreased power dissipation, small area, and high reusability. The speed of the DAC and the comparator limits the conversion time of a SAR-ADC. Here, we use a two-step architecture to relax the requirement of DAC and the comparator.
In chapter one, basic concepts and design consideration of delay-locked loops are introduced. Each block making up the DLL would be introduced briefly.
In chapter two, a three nonoverlapping phases clock generator is presented at first and the experimental results are given finally. With the nonoverlapping circuit, we can generate three nonoverlapping phases in the same frequency.
In chapter three, several performance metrics used to specify ADCs are described. Also, some different ADC architectures are discussed in chapter three.
In chapter four, the architecture of proposed two-step successive approximation ADC is illustrated. The experimental results are also shown at the end of this chapter. With the two-step architecture, the SAR-ADC has the property of low power consumption and small area.
In chapter five, we conclude the two works.
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