Automatic Multi-Cycle Path Assertion Property Generation in VLSI Designs
碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In this thesis, we proposed an effective method to verify the multi-cycle paths in a gate-level design with the SDC (Synopsis Design Constraint) timing constraints in the design setup file. We analyzed the usage of multi-cycle paths, and summarized it into sever...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76943192905263562864 |