| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In future SoC designs, on-chip-communication (OCC) is a very important issue, unlike traditional on-chip bus architecture, and we adopt on-chip network architecture to solve the problems caused by on-chip bus architecture, for example: wire complexity, crosstalk, data synchronization, can not support multiple clock domain, scalability, etc.
Focusing on the issue of supporting multiple clock domains, conventional SoC is supported by a single clock source and the total system performance will degrade when the numbers of IP on a system becomes larger. Thus, we adopt multiple clock sources; the reliable transmission method between multiple clock domains is asynchronous transmission technique. In several asynchronous transmission technologies, globally asynchronous locally synchronous (GALS) is a technique which can achieve transmitting data between different clock phase and different clock rate. In the same way, our research focus on transmitting data reliably between different clock domains, however, it improves the limitation of GALS technique.
Compared with conventional asynchronous transmission technique, our proposed asynchronous transmission technique has the characteristics of low latency, high data throughput and low latency. Unlike conventional asynchronous transmission technique, our transmitter has a flow control mechanism and receiver has an adaptive phase mechanism, the flow control mechanism is to control the transmission bandwidth and the adaptive phase mechanism is suitable for high clock rate, its function is to compensate the clock phase error. Based on the simulation results, our proposed asynchronous transmission technique can transfer data reliably between separate clock domains. Making a comparison with conventional GALS technique, our proposed asynchronous technique saves 50%~83% latency timing, improves 2x~6x data throughput and saves 40%~82% energy consumption.
We implement a basic OCN system platform, the platform is a 3×3 mesh topology and we integrate our proposed asynchronous technique into this platform, the simulation result shows the reliability and low latency that we expect. Finally, implementation on TSMC 0.18um 1P6M technology, the circuit area is 920×920um2, the maximum operation rate is 500MHz, and power consumption is 8mW.
|
|---|
