A 5-bit 10-GSample/s A/D Converter in 0.18-μm CMOS Technology

• Main Authors: Jian-Yu Ding, 丁建裕
• Other Authors: Jri Lee
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/31063426262433000591

碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === With the increasing use of digital computing and signal processing, the need of high-speed ADCs increases with time. Flash ADCs are still the architecture of choice, where maximum sampling rate and need no high resolution. For example, read-write channel of a disk drive systems, communication systems, microwave telescope array, and 10-GSamples/s microwave receiver are the cases. A 5-b 10-GSample/s analog-to-digital converter incorporates distributed sampling and digital offset calibration techniques. The sampling is accomplished by current-mode flipflops, eliminating the input-dependent distortions. The offset is calibrated digitally with a resolution of 5 bits. Fabricated in 0.18-μm CMOS technology, this converter achieves differential and integral nonlinearities of 0.4 and 0.6 LSB, respectively, and 4.05 effective bits at a sampling rate of 10 GHz. The circuit consumes 560 mW from a 1.8-V supply and occupies an area of 1.58 mm × 1.11 mm including pads.