Design and Implementation of All-Digital Fast-Locked DLL-Based Clock Generators

• Main Authors: Chuan-Kang Liang, 梁鵑伉
• Other Authors: 劉深淵
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/57613998803275086961

碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === To minimize timing skews and jitters of the clock signals, Delay-locked loops (DLLs) have been widely used. The DLLs benefit from the unconditional stability, fast locking process and better jitter performance compared with the PLLs. However, various intrinsic problems exist in a conventional DLL such as the narrow operation frequency range, harmonic locking issue, lack of frequency synthesis function, mismatch among delay stages, unsuppressed reference clock noise and so on. Besides introducing the basic concepts of the DLL, the block design issues in the analog DLLs and the control algorithm in the digital DLLs are also discussed. An all-digital ultra wide-range DLL-based clock generator with small area and an all-digital fast-locked programmable DLL-based frequency synthesizer are presented. The former is fabricated in a 0.18-um CMOS 1P6M technology and located with the area of 0.06mm2. Its operation range is from 1MHz to 520MHz. This is the widest range DLL with the smallest area known in the world. The latter is fabricated in 0.35um CMOS technology and occupies the active area of 0.216mm2. The clock multiplication ratio is programmed from 2 to 15. The frequency range of the input and output clocks are 4~200MHz and 60~450MHz, respectively. This is the first all-digital DLL-based frequency synthesizer in the world.