Hardware IP interface design and synthesis for System-on-a-Chip
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 94 === Hardware interface design is an elaborative step during intellectual property IP integration. Efficient System-on-a-Chip SoC design depends heavily on IP reuse and high level synthesis. As components of these two methods often have different communication interf...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70644520668892147902 |