| Summary: | 博士 === 國立臺灣大學 === 資訊工程學研究所 === 94 === NAND flash memory is widely adopted as an alternative for storage system designs in mobile/portable devices because of its nature in non-volatility, shock-resistance, and low power consumption. It is also considered being low cost, compared to SRAM or DRAM, and having good performance, compared to disks. In this thesis, a reliability enhancement layer is designed for flash memory with
single or multiple bits per cell to resolve the possibility of false identification on the logic states of flash-memory cells. It aims at providing a way to tune up the system reliability and performance, depending on the needs of different vendors. When the system performance is considered, we propose a highly efficient design for the identification of hot data for flash-memory management. It is to not only boost the system performance but also reduce the overheads and improve the efficiency in garbage collection and wear-levelling. This thesis is concluded by the exploring of device designs with mechanical and flash components. A cache layer is presented to serve as a flash-memory cache for disks. An efficient LBA lookup mechanism and a garbage collection strategy are proposed. The capability of the proposed approaches were evaluated by a series of experiments to demonstrate the effectiveness of the designs.
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