A 2nd-Order Multi-bit Lowpass Delta-Sigma Modulator for Wireless LAN
碩士 === 國立臺灣海洋大學 === 電機工程學系 === 94 === In recent years, many different applications and standards are appeared because of the rapidly promotion on digital communication. Therefore, there are many considerations on power effect with cellular phone and wireless communication, so we using direct-convers...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66264887948230231012 |
| Summary: | 碩士 === 國立臺灣海洋大學 === 電機工程學系 === 94 === In recent years, many different applications and standards are appeared because of the rapidly promotion on digital communication. Therefore, there are many considerations on power effect with cellular phone and wireless communication, so we using direct-conversion receiver. It doesn’t need mid-band filter but must use a high input-bandwidth ADC. So ADC became a very important device in many different standards.
A high input bandwidth multi-bit Delta-Sigma modulator for Bluetooth System applications is designed thesis. Multi-bit Delta-Sigma modulator can achieve 10-bit resolution and 1MHz signal bandwidth when oversampling rate of 16 is used. Fully differential switched capacitor is used to accomplish the modulator. The quantizer is made by a 17-level Flash ADC. Dynamic element matching technique is used to minimize the capacitor mismatch problem. Data weighted averaging (DWA) provides noise shaping for the nonlinear error on feedback path of DAC. The error and noises produced during the process of transferring digital to analog are suppressed and the efficiency of multi-bit Delta-Sigma modulator is effectively improved by way of eliminating quantization error. Our work is implemented in TSMC 0.35um 2P4M CMOS process for application of 1MHz bandwidth in Bluetooth communication system.
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