An Area-Efficient Intra Predictor for High Resolution H.264/MPEG-4 AVC Decoding

• Main Authors: Yung-Hung Chang, 張元鴻
• Other Authors: Youn-Long Lin
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/17012267042889175338

碩士 === 國立清華大學 === 資訊工程學系 === 94 === We propose an area-efficient architecture for intra prediction in H.264/MPEG-4 AVC video decoding. There are 17 possible prediction modes defining how each pixel is predicted. However, in the encoded bitstream only one mode is used to predict luma component and another for chroma component. Therefore, resource sharing is the key to efficient implementation of hardwired intra predictor for low cost and high resolution applications. We propose a novel data routing and reuse scheme to implement our intra predictor. It takes only 127 cycles to predict a macroblock. Our design is economical (18.8K gates) and high performance (100MHz @ TSMC 0.13μm). It can support real-time decoding of 3680 x 1536 @ 30 fps. Our design has passed both cell-based and FPGA-based gate-level simulation for a large set of test video sequences and has been successfully integrated into a hardwired main profile decoder on a multimedia SOC platform.