| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 94 === High-performance and low-power VLIW DSP processors are increasingly
deployed on embedded devices to process video and multimedia
applications. For reducing power and cost in designs of VLIW DSP
processors, distributed register files and multi-bank register
architectures are being adopted to reduce the amount of read/write
ports in register files. This presents new challenges for devising
compiler optimization schemes for such architectures. In our
research work, we address the compiler optimization issues for PAC
architecture, which is a 5-way issue DSP processor with distributed
register files. We show how to support an important class of
compiler optimization problems, known as copy propagations, for such
architectures. We illustrate that a naive deployment of copy
propagations in embedded VLIW DSP processors with distributed files
might result in performance anomaly. In our proposed scheme, we
derive communication cost models by cluster distance, register port
pressures, and the movement type of register sets. The cost models
are used to guide the data flow analysis for supporting copy
propagations over PAC architectures. Experimental results show that
our schemes are effective to prevent performance anomaly with copy
propagations over embedded VLIW DSP processors with distributed
files.
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