Engineering Change Using Spare Cells
碩士 === 國立清華大學 === 資訊工程學系 === 94 === In the VLSI design process, the design change happens often due to new specifications or design constraint violations. This correction process for the new specification is known as engineering change (EC). Practically, the EC problem is usually resolved by using s...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58839970942898459918 |