A Low-power High-speed 8-bit Pipelining CLA Design Using Dual Threshold Voltage Domino Logic and Low-cost Digital I/Q Separator for DVB-T

A Low-power High-speed 8-bit Pipelining CLA Design Using Dual Threshold Voltage Domino Logic and Low-cost Digital I/Q Separator for DVB-T

碩士 === 國立中山大學 === 電機工程學系研究所 === 94 === This thesis includes two topics. One is a low-power high-speed 8-bit pipelining CLA design using dual threshold voltage (dual- Vth) domino logic. The other is a low-cost digital I/Q separator for DVB-T receivers. A high speed and low power 8-bit CLA using du...

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Bibliographic Details
Main Authors:	Tsai-Wen Cheng, 鄭採文
Other Authors:	Chua-Chin Wang
Format:	Others
Language:	zh-TW
Published:	2006
Online Access:	http://ndltd.ncl.edu.tw/handle/15732239599200597417

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