On Switch Factor Based Analysis of Coupled RLC Interconnects

• Main Authors: Jia-Ming Chen, 陳家銘
• Other Authors: Po-Hao Chang
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/75725811304590625966

碩士 === 國立東華大學 === 電機工程學系 === 94 === In recent years, the density of the components in the integrated circuit has been growing more and more. Thousands upon thousands of transistors have been put on one chip. SoC (System on a Chip) is a new trend of the VLSI design in the deep submicron technique and is under intensive investigation. Nevertheless, it still has to face several problems, such as the volume issue, thermal problem, power consumption, noise, etc. In the SoC, several kinds of signals transmit in interconnects. If two of the path lines get too closer, there will be some noise produced when signals passing through one or two lines. This noise is called the “Crosstalk Noise”. Because the space for layout in the SoC becomes smaller, the coupling capacitance becomes larger. Since the source voltages in our interconnects become smaller, the propagation delay as the effect on the entire circuit by the crosstalk noise is very important and needs further investigation. The propagation delay is the main research focus in this thesis. The most accurate but time consuming approach is to use HSPICE simulation to perform the analysis. We propose a new method to obtain the equivalent circuit, and it is of a closed form which is suitable for the coupled circuit composed of multiple coupling capacitors and mutual inductors. In one general coupled circuit with two lines in which there are different resistances and capacitances between line and ground and different slopes of the source voltages, we refer to the assuming parameter in the other paper and use our approach to estimate the propagation delay. By comparing with the result obtained from simulating the circuit with HSPICE, our result shows that the error rates are within 10%. The average error rate is around 5%.