| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 94 === ISO proposed JPEG2000 for the lossless compression standard. The major difference between JPEG and JPEG2000 is transform coding. JPEG2000 uses discrete wavelet transform (DWT) to solve discrete cosine transform (DCT) disadvantages (blocking artifact). DWT provides a new method that transforms time domain to frequency domain for signal processing. Furthermore, it assigns the frequency domains to subbands. DWT needs the temporary storage to store the subbands. Thus, we need a large store space. Furthermore, DWT spends more computing time than DCT. Thus, we use hardware design to implement it. In this thesis, we present an efficient VLSI architecture for high-performance 2-D Lifting-based DWT. Our proposed architecture includes the parallel Horizontal Processor (HP) and the pipelined Vertical Processor (VP). Our HP module utilizes 16-bit scan bus which can compute 2 row-data in one cycle, so that we can begin column-operation in the third cycle. Thus, our design can reduce internal memory in column-operation.
Our proposed architecture works in pipeline, and the required memory size is 2N+20 (including the pipeline registers). Furthermore, our control unit is simple, so that we can reduce latency. When the image size is N×N, we need approximately clock cycles for computing one level of 2-D DWT. We present a DWT architecture which has lower hardware cost and higher performance than other proposed designs. Our DWT can operate at around 780 MHz. The gate count is 21376 and the temporary storage size (internal memory) is 2N+20. Our future work will be trying to apply it on 9/7 filter DWT and watermark encoding.
|
|---|
