Chip Design and Implementation of CMOS Mixers for WCDMA and UWB Applications

• Main Authors: De-Mao Chen, 陳德茂
• Other Authors: Zhi-Ming Lin
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/12786170531082706453

碩士 === 國立彰化師範大學 === 電機工程學系 === 94 === In this thesis, the designed mixers are operated individually in WCDMA transmitter and UWB receiver. A 2GHz CMOS direct-conversion mixer with current-reuse and multiple-gated-transistors (MGTR) topologies is designed for application in a WCDMA transmitter. The current-reuse topology is used to overcome the limitation of supply voltage and the MGTR topology is used to increase the linearity of third-order intercept point in the differential input transconductance stage of the mixer. The differential RF signal is converted into single-end signal by a differential-to-single circuit. The mixer is designed and implemented in UMC 0.18 µm CMOS technology. With -30 dBm power for 10 MHz input IF, 0 dBm power for 1.94 GHz input LO and 1.95 GHz output RF, the test chip achieved: 5.75 dB conversion gain, 10 dBm OIP3, 6.2 dBm IIP3, and 5.35 mW power consumption for 1 V supply voltage. Another fully integrated 3 to 5 GHz CMOS mixer is also designed for UWB system. The designed mixer utilizes a dynamic injection circuit to reduce noise figure. In order to adjust the conversion gain, linearity, and noise figure easily, we connect a capacitor and a resistor in series between the drain and the gate of a NMOS transistor. An active balun which converts the single-ended input signals to differential signals for 3 to 5 GHz is also integrated in the chip. With -30 dBm for 3 to 5 GHz input RF and 0 dBm for 3 to 5 GHz input LO, the measured chip achieved 5.2 ~ 8.8 dB conversion gain, -2.5 ~ 3.7 dBm IIP3 and -11 ~ -7.8 dBm P1dB for 1.8 V supply voltage.