| Summary: | 碩士 === 國立彰化師範大學 === 電機工程學系 === 94 === ABSTRACT
In this thesis, we propose a low power direct digital frequency synthesizer (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. The ROM size of the proposed architecture is 25% less than that of conventional two-level table. The hardware complexity of the new DDFS architecture compared to the traditional two-level table DDFS can be omitted one multiplier.
In TSMC 0.35-μm cell-based flow, the architecture of the DDFS is synthesized with a SFDR of -80dB, runs up to 100MHz and consumes 81-mW at 3.0v. The power efficiency is 0.81-mW/MHz, which represents an enhancement of more than 38% compared to the conventional DDFS.
Keywords: DDFS, Low power, VLSI, ADPLL.
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