A nano-thick layer transfer technology

• Main Authors: Chao-Liang Chang, 張朝喨
• Other Authors: Tien-Hsi Lee
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/14340458413800845957

碩士 === 國立中央大學 === 機械工程研究所 === 94 === As CMOS devices scale down to 90nm node or below, parasitic capacitance and low current leakage will increase. Therefore, the unique properties of silicon-on-insulator (SOI) structure are able to solve above problems, because SOI wafers consist of a layer of single crystalline Si that is separated from Si substrate by an insulating film of SiO2. Building IC devices in this top Si film effect many advantages such as reducing capacitance and leakage and no latch-up , especially for the design of high speed and low power consumption devices. The issue of quality of massive production doesn’t also make SOI wafers a mainsfrain material to substitute for bulk silicon. But numerous advanced SOI fabricating techniques have been invented nowadays; all these will upgrade the quality and lessen the price of SOI wafers. In this study, one dimensional nanostructure materials on a desired substrate fabricated by a hydrogen ion-exfoliation-based wafer bonding approach. The nano-scale defining thickness is exactly achieved by the employment of polysilicon depth as implant sacrificial layer. After hydrogen ion implantation, the as-implanted wafer was contained a hydrogen-rich buried layer less than 100 nm. Prior to the as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet chemical etching method. A nanothick single crystal silicon layer was than thermal successfully transferred from a device wafer onto a handle wafer after 10-minute microwave irradiation. The thickness of the final transferred silicon layer measured by transmission electron microscopy (TEM) was 100 nm.