| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 94 === With the process technology innovating rapidly, the device size is continuing to scale down. In SoC era, traditional design techniques must be modified to solve the integration problems with over million gate counts in a single chip. The major design challenge is the issue of co-simulation speed to verify a mixed-signal system. Integrating all blocks at layout-level and running the low-level post-layout simulation become almost infeasible for modern large designs. Moreover, such traditional simulator like SPICE requires too much simulation time such that it cannot meet the designer’s demand due to the pressure of time to market. Therefore, building a behavioral model is necessary so that we could get the simulation results very soon.
In this thesis, we use hardware description language Verilog-A to build the behavioral models of ΣΔDAC and use them to estimate and handle these two integration issues. We present a bottom-up extraction flow to extract the characteristic parameters for ΣΔDAC behavioral models in a short time. Then, we adjust these parameters to consider the non-ideal effects such that the behavioral model could be much closer to the simulation results of SPICE.
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