| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 94 === With increasing complexity of circuit design in the SoC period, designers have to spend more time for circuit simulation. In order to simulate the mixed signal circuits rapidly, we are going to describe the circuits in behavioral level instead of circuit level. In the past years, SPICE is a basic simulator of design and verification when developing analog or mixed-signal circuits. However, with the advance of semiconductor technology and rapid time-to-market requirement, SPICE simulator can not satisfy the requirements of advanced circuit design any more. In this thesis, we propose a module of behavioral level using Verilog-A to describe the second order sigma-delta modulator. Meanwhile, we use a bottom-up verification method to extract its non-ideal effects. Then, we establish a standard parameter extraction flow to make the result of our behavioral model for the second order sigma-delta modulator can be more close to the actual simulation results of transistor level. Most importantly, our method, which is called back calibration, can be used in various second order sigma-delta modulators.
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