| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 94 === When the efficiency of the speed with the very large-scale integrated (VSLI) circuit increases fast, there are more and more transistors in the unit area, because of these, the timing delay is promoted relatively. The accurate clock is necessary in chip design, especially the SOC (System-on-chip) design is developed, however, there is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. In this reason, the phase locked loop (PLL) is used to correct the clock phase when the major clock inputs the sub-circuit, and it can lead the operation clock of the sub-circuit into the same clock phase.
The challenge in designing the PLL, besides the improvement of the performance like low jitter, fast locking, and low power consumption, the restrictions of fixed loop parameters make the normal PLL just used in the specific standards, and that reduces the applications of the PLL. The loop parameters such as loop bandwidth and phase margin determine jitter performance and system stability. According to the restrictions of the PLL, this thesis employs formula derives to find the relationship between the loop parameters. Furthermore, we propose the architecture of PLL that can be adjusted to minimize jitter and to guarantee the stability with the reference frequency and multiplication factor. We use switch-capacitor equivalent resistor and programmable inverse-linear current mirror to adjust the current of charge pump and the resistor of loop filter in PLL for wide range operation. In the discussion of leakage current and large multiplication of PLL for 90nm process, we use the charge pump with OP amp to improve the effect.
We use the UMC 90nm 1P9M CMOS process with 1-voltage supply voltage in this thesis. The measurement results is that the oscillator output of this PLL is locked between 100MHz and 1GHz when the input reference frequency is 1MHz-50MHz and multiplication factor is 2-1023 and the peak-to-peak jitter is less than 15.5% of output frequency. The total power consumption of the proposed PLL is 22mW at 20 multiplication factor, 1GHz operation frequency.
|
|---|
