| Summary: | 博士 === 國立中央大學 === 電機工程研究所 === 94 === In the recent years, the semiconductor manufacturing technology proceeded at a very rapid pace. The simulation of device’s characteristic is always used to reduce the manufacturing cost and time in the semiconductor industry. Therefore, it is a very important task to develop the device simulation. However, it requires a considerably huge amount of memory size and calculation time in 2-D or 3-D device simulation. Therefore, we propose the device partition method (DPM), small-resistance coupling (SRC) method, and quasi-3D technique to improve our mixed-level device and circuit simulator in this dissertation. In DPM, we have demonstrated that the lower consumption of memory accompanies the larger part number of DPM in 2-D or 3-D device simulation. Besides, we have also demonstrated that the calculation time decreases as the part number of DPM increases in 3-D device simulation. Furthermore, we have proposed SRC method to improve the limit on the discussion of the complicated mixed-level device and circuit simulation using the band matrix solver. In this dissertation, we also use SRC method to study the negative-differential-resistance oscillator, crystal oscillator, and CMOS ring oscillator circuits. In the quasi-3D device simulation, because the quasi-Fermi level of majority carrier is nearly constant, the voltage source can be connected to the majority carrier circuit. Therefore, we can obtain the solution that is close to the conventional 3-D device simulator. In the application of quasi 3-D device simulation, we also use the quasi-3D technique to study the body-tied SOI MOSFET and dynamic threshold voltage MOSFET (DTMOS). Finally, we use the equivalent circuit models for the vertical and horizontal integrations to study the flat-band voltage of non-ideal MOS-C.
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