Simulation and Analysis of MOSFETs in SOI Substrates
碩士 === 國立交通大學 === 理學院碩士在職專班應用科技學程 === 94 === In this study, we designed, simulated and analyzed the device characterization of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). The effects of doping concenteation gradient,spacer length, gate length, and silicon...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/77291506435729121759 |
| Summary: | 碩士 === 國立交通大學 === 理學院碩士在職專班應用科技學程 === 94 === In this study, we designed, simulated and analyzed the device characterization of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). The effects of doping concenteation gradient,spacer length, gate length, and silicon body thickness to the device performance are investigated by comparing the on- and off-currents of simulated SOI MOSFETs with the high performance (HP) and low operating power (LOP) specifications of International Technology Roadmap for Semiconductors (ITRS). We found the effects from spacer length and doping concenteation gradient can be trade-off and their effects were much less than those from the other two parameters. Scaling down the gate length can increase device speed but the accomapnied large leakage current may rule out the merit of speed improvement. After all, the thickness of silicon body is the key point to device performance enhancement based on both HP and LOP specifications.
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