Design of Frequency Synthesizer for GPS Receivers

• Main Authors: Shin-Liang Hout, 侯信良
• Other Authors: Mu-Huo Cheng
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/28974283879448381302

碩士 === 國立交通大學 === 電機與控制工程系所 === 94 === In this thesis we design a frequency synthesizer which can generate a steady oscillating signal of 1.575GHz for GPS receivers. This frequency synthesizer uses a quartz for oscillation at 24.61MHz as the reference signal; this signal then is used as the input of a phase-locked loop composed of a phase detector, a loop filter, a voltage-controlled oscillator, and a divider with division ratio of 64 (N=64). When the loop converges, the VCO output signal frequency will equal 64 times of 24.61MHz. All functional blocks of this frequency synthesizer are realized by circuits of the differential type in order to lower the noise effect on the high-frequency output signal. The TSMC 0.35 um BiCMOS Mixed Signal SiGe 3P3M process is used to implement the frequency synthesizer; its model parameters are used to simulate the dynamic behaviors and obtain the performance parameters such as the phase noise and the phase jitter. The consumption power of the frequency synthesizer is 38.5mW with the 3.3V power supply. A wide range of VCO operation frequency, 1.1GHz-2.8GHz, is designed to ensure that the VCO still can generate the desired frequency even when the process conditions vary. Simulation results demonstrate that the synthesizer obtains a steady output signal under different corner models. The phase noise is obtained to be -106dBc/Hz.