| Summary: | 碩士 === 國立交通大學 === 資訊學院碩士在職專班資訊組 === 94 === ASIP(Application Instruction Set Processor) are commonly used in today’s SOC design. Some SOC chips use more then one ASIPs. The most difference between ASIP and a general purpose CPU is that ASIP usually execute instructions fixed in chip instead of different programs in RAM. To optimize the chip area and performance, ASIP tool can let user generate own instruction set, pipe line state, function unit. And generate RTL code, compiler, simulator of the dedicated ASIP to be used.
We select the ASIP meister tool (http://www.eda-meister.org/) from Osaka University as our ASIP design tool. Which can generate VHDL source code and C compiler generator files for COSY compiler generator (http://www.ace.nl) . The ASIP meister use graphic interface in defining instructions and pipe line stages. And can estimate the gate count, power, performance before chip implementation. We will define a 32-bit RISC CPU, and generate RTL code and implement real chip. For verify ASIP design flow and the ASIP meister tool. For SOC design such as network, graphic, digital, … applications that need ASIPs, the ASIP methodology can be used.
Our ASIP is a 5 stage 32bit RISC, and the instruction set is from open source OR1K (http://www.opencores.org/projects.cgi/web/or1k). Since we could not get the COSY compiler generator, we have to use the OR1K GNU C compiler. So we are not able to refine instructions, but we still can evaluate the ASIP approach for a CPU design.
After the RTL code, we will prepare the chip implementation. We will use UMC .18 um cell lib to synthesis by Synopsis, and other tools from CIC to do scan chain insert, APR(Auto Place and Route), DRC/LVS for chip tape out requirement by CIC.
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