A New Paradigm for Diagnosing Hold-Time Faults in Scan Chains
碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 94 === As the continuing improvement on the semiconductor process technology and EDA (Electronic Design Automation) industry, it allows the current digital IC design to put more functions within the limited silicon die area. However, a million-gate- count design ma...
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| Format: | Others |
| Language: | zh-TW |
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2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40959614320992669060 |