| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 94 === In the world of modern wireless communication, phase-locked loop (PLL) based frequency synthesizers have played an important role in RF front-ends. As the wireless standards evolve, it presents an increasing challenge to meet the stringent requirements of low jitter or phase noise, fast settling time, and low power in PLL designs, which involve a lot of design issues and trade-offs. Two crucial design issues, dead-zone and blind-zone are detrimental to the performance of PLLs, increasing the timing jitter and slowing the settling speed, respectively. In particular, the decrease of one of them may cause the increase of the other.
To overcome these issues, the research described in this thesis focuses on the design of phase-frequency detectors (PFDs). A new way to eliminate the dead-zone as well as the blind-zone has been founded and developed, whereby a novel and robust fast frequency-acquisition PFD is proposed. A 2.36~2.95-GHz integer-N frequency synthesizer including our proposed PFD is implemented in a standard TSMC 0.18-μm CMOS process. Simulation results reveal that the frequency synthesizer using our proposed PFD shows a locking time of 1.93μs, which is an improvement of up to 25% over that using a conventional PFD, while consuming 25.9mW at a 1.8V supply in the case of starting at 2.36 GHz and locking at 2.8 GHz. In addition, as compared with other PFD architectures, our proposed PFD manifests itself as a robust design for higher operating frequency, and neither dead-zone nor blind-zone.
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