| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 94 === The thesis consists of two part: voltage-controlled oscillator(VCO) and phase-locked loop(PLL). Utilize TSMC 0.18μm RF CMOS Technology to be made high-frequency voltage-controlled oscillator and phase-locked loop which can be applied to UWB system.
The first part designs two kinds of quadrature VCOs(QVCOs) which have different circuit characteristics. The first kind of QVCO adopts complementary cross-coupled pair. The measured tunning range is 6.1GHz~6.5GHz, phase noise is -110dBc/Hz at 1MHz offset , power consumption is 14.4mW, and output power is -17dBm under 1.8V supply. The second kind of QVCO adopts current-reuse topology. The measured tuning range is 6.4GHz~6.7GHz, phase noise is -106 dBc/Hz at 1MHz offset, power consumption is 6.8mW, and output power is -11dBm under 1.4V supply.
The second part designs two kinds of PLLs that can be applied to UWB system. PLLs output frequency is 7.92GHz and 3.96GHz, including I/Q signals. The first kind of PLL adopts current mode logic(CML) divider at the 1st stage divider. Its avantage is perfect I/Q signal output but power consumption is large. The whole loop simulated power dissipation is 13.5mW, which CML divider is 9.9mW. The second kind of PLL uses a true single phase clock(TSPC) divider at 1st stage divider. Its advantage is low power consumption but output signal I/Q characteristic depends on its input signals. The whole loop simulated power dissipation is 6.8mW.
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