The Study of SAW Oscillators Implemented by CMOS Technology
碩士 === 國立交通大學 === 電信工程系所 === 94 === In this thesis, saw oscillators are studied. The Colpitts structure is adopted. The focus is on the differences of negative resistance between one-stage and three-stage inverter. The analytical results of the negative resistance using one stage inverter are develo...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85508276113747138531 |
| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 94 === In this thesis, saw oscillators are studied. The Colpitts structure is adopted. The focus is on the differences of negative resistance between one-stage and three-stage inverter. The analytical results of the negative resistance using one stage inverter are developed, which provides a direction of device optimization. The negative resistance is significantly enhanced by employing three-stage amplifier to overcome the parasitic effect from saw device. Even under high parasitic capacitor and high frequency operation, better negative resistance can be achieved. The saw oscillator at 622MHz with the PECL output is implemented by TSMC 0.35 um process. The dependence of output power on the input dc level of PECL is also discussed.
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