Research and Design of Low Voltage High PSRR Bandgap Circuit

• Main Authors: Chi-Kang Wang, 王冀康
• Other Authors: Jyh-Chyurn Guo
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/22129120069364438939

碩士 === 國立交通大學 === 電子工程系所 === 94 === OP-Amplifier plays an important role in the bandgap circuits. According to the theory, the OPA which use nMOS as the input stage will get a better voltage gain than that using pMOS as the input stage. Besides, for OPA using pMOS as the input stage, the voltage offset on the input port will be multiplied largely. By contrast, for bandgap circuits that use nMOS as the OPA’s input stage, the voltage offset on the OPA’s input port will not be multiplied as largely as that with pMOS as the input stage. However, because of the limitation of conventional bandgap circuit for providing the OPA’s input common mode voltage, most bandgap circuit was designed by using pMOS as the input stage in the past. So we modify the conventional bandgap core circuit topology to create new type of bandgap circuit topologies. The new types of topologies can drive OPA that use nMOS as the input stage. In this thesis, four kinds of low voltage-operated bandgap reference (BGR) circuits in CMOS technology, with high PSRR (power supply rejection ratio) are presented. Two of those proposed circuits use the OP-Amplifier in which the input stages are composed of pMOS. The others use nMOS as the input stage of the OP-Amplifier. In this study, TSMC 0.18μm and 0.35μm CMOS process were adopted for circuit fabrication and verification. Type A and B were implemented by using 0.18μm process in which pMOS differential pair were adopted for type A while nMOS differential pair were employed for type B. Regarding type C and D which were fabricated by 0.35μm process, type C adopted pMOS differential pair while type D employed nMOS differential pair. The experimental results show that it is possible to achieve 700mV reference voltage with low power supply voltage at 1.1V and a well-controlled temperature compensation performance. For types A and B implemented by 0.18μm technology, the output reference voltages were achieved at 772mV and 737mV corresponding to the minimum supply voltage at 1.10V. PSRR under varying frequencies were achieved at -56 / -51 dB, -29 / -33 dB and -15.2 / -26 dB corresponding to 1K, 10K, and 100KHz for type A / B respectively. The effective temperature coefficient (TC(eff)) was as high as 140 ppm/℃ due to deviation of resistance ratio caused by the asymmetric process variation between diffusion resistors and poly-Si resistors. As for type C and D fabricated by 0.35μm technology, the output reference voltages were achieved at 766mV and 829mV corresponding to the minimum supply voltage at 1.3 / 1.1V. PSRR under varying frequencies were achieved at -18 / -25 dB, -2.7 / -10 dB and -0.1 / -0.42 dB corresponding to 1K, 10K, and 100KHz for type C / D respectively. The PSRR is not as good as that predicted by simulation due to suspected parasitic resistance and capacitance effects. TC(eff) were achieved as 90.2 / 34.1 ppm/℃ for type C / D at Vdd = 1.3V, which shows significant improvement as compared with type A / B to adoption of diffusion resistors over the whole circuit chip. Based on the simulation and measurement results, we make the conclusion that BGR circuits which use nMOS as the OP-Amplifier’s differential pair provide better performance and enable lower cost due to reduced chip area.