High-Performance Reconfigurable Sub-Word Parallel Multiplier-Accumulator Design
碩士 === 國立交通大學 === 電子工程系所 === 94 === This thesis presents the design methodology of a high-performance reconfigurable multiplier-accumulator (MAC) capable of supporting sub-word parallelism (SWP) and additional features such as mixed-mode operation and flexible sub-word combination and mode assignmen...
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| Format: | Others |
| Language: | en_US |
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2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70513499807532928334 |