| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 94 === In this thesis, two kinds of devices (MOSFETs and TFTs) have been fabricated to examine the films effect and integration of device characteristics. First, the effects of polish pad conditions and slurry solid contents on SiGe chemical mechanical polishing (CMP) process were investigated. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. By adding the surfactant (TMAH) and chelating agent (EDTA) into the diluted ammonium solution, removal efficiency of particles and metallic impurities is increased. The smooth strained-Si surface on flatten Si0.8Ge0.2 buffer layer of 0.6 nm can be achieved. The electrical performances of capacitors such as breakdown voltage, leakage current and Qbd are significantly improved for post-CMP cleaning. Furthermore, the optimal condition of SC1+TE sample has increased about 10 % in drive current. This post-CMP cleaning process is useful for planarization of strain-relaxed SiGe virtual substrates in MOSFET application.Next, we have demonstrated the fabrication of Dynamic Threshold voltage MOSFET (DTMOS) using the Si1-yCy (y=0.005) incorporation inerlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si1-yCy interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. The excellent performances obtained in the Si1-yCy interlayer DTMOS are due to both the same substrate doping concentration and lower channel surface impurity concentration. So the surface impurity scattering could be reduces. We have successfully achieved the low threshold voltage and heavily doped substrate DTMOS with superior characteristics in terms of the higher transconductance (1.2×Gm) and saturation current (1.8×ID). It appears to be a very promising technology for nano-scale device and ultra-low voltage application.Then, we demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon Thin-Film Transistors (poly-Si TFTs) with different numbers of channel stripes. The device’s electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. Therefore, for the fabrication of highly reliable devices and to improve the yield of multi-channel TFTs, the channel structures must be carefully designed.Finally, the improvement of polycrystalline silicon germanium thin-film transistors (poly-SiGe TFTs) using NH3 passivation and CMP process was examined. Experimental results indicated that NH3 passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibit higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio due to the smooth poly-SiGe interface. The results clearly show that by employing the plasma and CMP steps, significant improvement in the poly-SiGe TFTs with low thermal budget can be achieved.
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