| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 94 === This dissertation investigates the channel decoders from algorithms to architecture designs and
circuit implementation. Three different decoding schemes are studied, including the algebraic, the
probabilistic, and the iterative decoding algorithms.
The Reed-Solomon code based on the algebraic decoding is exploited to many system specifications.
We apply the Montgomery multiplication algorithm to the universal finite field multiplier;
as a result, the arithmetic units are capable of different finite field definitions. The Reed-Solomon
decoder is constructed based on the proposed arithmetic operations and modified for less complexity.
Hence the decoder can be applied to many systems without circuit modification. The
chip implementation results show that the overhead due to the universality is no more than 100%.
Moreover, the decoding speed from the measurement can meet most current or future applications.
The maximum-likelihood decoding, Viterbi decoding algorithm, for the convolutional code
is widely used in many digital communications. The low power design techniques for the Viterbi
decoder are proposed for the dynamically survivormemory access and the datapath transformation.
The survivor memory unit with the path merging and the path prediction algorithms can adaptively
adjust the truncation length according to the channel conditions. Combining a cache buffer, we
can avoid many read operations in the memory, leading less power consumption. On the other
hand, we also transform the add-compare-select (ACS) operation to compare-select-add (CSA) for
less computations resulting in lower cost as well as lower power dissipation. The implementation
results indicate about 30%~40% power reduction is accomplished with the proposed architecture.
The high speed and area efficient Viterbi decoder is also presented with the two-dimensional ACS
structure. The decoder on the radix-16 trellis is implemented and shown to achieve over 1Gb/s
data throughput.
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We further conduct the research into the iterative decoding based turbo codes and low-density
parity-check (LDPC) codes. The turbo decoder is considered in the mobile communication system
with large interleaver size. The simple decoder architecture is utilized for cost consideration, and
the memory is optimized for power consumption. The unified turbo and Viterbi decoder chip is
also shown to achieve better energy efficiency. The LDPC decoder is designed for high speed
applications for its highly parallelizable decoding algorithm. Because of the irregular parity check
matrix and the large number of processing elements, the register exchange memory is introduced
to accommodate the large message passing in the decoder. As a result, the circuit implementation
leads to a high decoding speed, which is 5.92Gb/s, and area efficient decoder chip whose chip
density is larger than 70%.
In this dissertation, the research includes different channel decoding schemes as well as their
implementation for applications. Exploring the system requirements, we provide various design
methods and analysis for the decoders. Finally, the circuits are realized for measurement or analysis,
and the results reveal the positive consequence as expected.
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