Design Low Power Active Balun and Mixer for Ultra-Wideband Application

• Main Authors: Ta-Tao Hsu, 徐達道
• Other Authors: Chien-Nan Kuo
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/17771967520835208566

碩士 === 國立交通大學 === 電子工程系所 === 94 === The aim in this thesis is mainly based on the design of active balun and mixer in the receiver front end of ultra-wideband system using standard 0.18um CMOS process. Also, a low power low voltage narrow band front end is composed of a new mixer and a low noise amplifier. Two low power UWB active baluns, one low power mixer combined with a low power active balun and one low power low voltage front end were verified through 4 individual chips. In the first chip, an 8 GHz Low Power Ultra-Wideband Active Balun is analyzed and designed. We employ a new topology to design active balun and greatly reduce power consumption and extend the available bandwidth. Measured data show that the bandwidth extends to 8 GHz, gain difference is less than 2 dB, phase difference is less than 3 degree and differential gain has flat gain about -2 dB while consuming 1.5mW. In the second chip, an ultra wide band low power tunable active balun for process variation compensation is analyzed and designed. A tunable active resister is adopted to improve the first chip. Measured data show that the active balun has a tunable function for process variation compensation is its most important property. In the third chip, a new design of a low power low voltage mixer is combined with an active balun of the first chip. All transistors in the mixer are biased in the subthreshold region to approach low power application. Use large resisters about 800 Ω as output loading to have high conversion gain and the gain of balun and mixer compensate each other to form a flat gain from 6 to 10 GHz. Measured data show that the flat conversion gain is 9.5 dB ± 1.5 dB from 6 GHz to 10 GHz, NF is about 15 dB and IIP3 is about 3 dBm while consuming 1.5mW. In the final chip, a 5~6 GHz low power receiver front-end circuit is analyzed and designed. Employ the mixer of the third chip and modify the mixer from double balance to single balance. The single input mixer combines with a single output LNA and all supply voltages are reduced to 1 V to form the 5 ~ 6 GHz 1V low power receiver front-end circuit. Measured data show that the max conversion gain is 25 dB at 5 GHz, 3 dB bandwidth is about 1 GHz, NF is about 10 dB and IIP3 is about -6 dBm while consuming 0.8mW.