| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 94 === As the IC fabrication technology advances, the need for high-bandwidth and low-latency inter-chip data transfer has also increased. Most of time, the key limitation of a whole system is the maximum data amounts of the transmission interface circuit transmitted in each unit time.
This thesis describes the design of a high-speed serial link I/O interface. We have devoted to design two types of the transceiver at 1.6Gbps.The difference between Type 1 transceiver and Type 2 transceiver is the frequency of the output clock. Type 1 transceiver transfers 100MHz clock; Type 2 transceiver transfers 800MHz clock.
The transmitter is composed of a eight-phase PLL, PRBS circuits, 4-1 multiplexers, clock process circuit and an output data and clock driver. Among these devices, the input frequency of the eight-phase PLL is 100MHz, and it outputs eight uniformly distributed clocks with 400 GHz frequency. The PLL consists of a Phase/Frequency Detector, a Charge Pump, a Loop Filter, a four-stage differential VCO and a divided-by-four divider. It offers the PRBS and the 4-1 multiplexer with four uniformly distributed clocks to convert parallel pseudo-data into serial stream. Then, the serial data is transmitted by an output data driver. In the end, the transmitter drives the serial data and clock onto the transmission bus.
The receiver uses the comparator with hysteresis to amplify the incoming data and clock to full swing. Then, Type 1 receiver uses 100MHz clock to generate four uniformly distributed clocks with 400 GHz frequency to sample data. Type 2 receiver uses 800MHz
operating at half of the input data rate Finally, the de-multiplexer converts the serial outputs to four parallel data channels.
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