The Design and Analysis of a CMOS 8bit 50MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立交通大學 === 電子工程系所 === 94 === The thesis describes the design of a 3.3 V, 8-bit, 50M sample/s CMOS pipelined analog-to-digital converter (ADC) implemented by simulation with 0.35um double-poly four-metal process. The component in the ADC is the residue amplifier, the dynamic comparator, the fl...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/4zw5xs |
| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 94 === The thesis describes the design of a 3.3 V, 8-bit, 50M sample/s CMOS pipelined analog-to-digital converter (ADC) implemented by simulation with 0.35um double-poly four-metal process. The component in the ADC is the residue amplifier, the dynamic comparator, the flip-flop, the adder and the clock generator. The prototype ADC is implemented by an input sample-and-hold circuit (S/H), 6 identical 1.5-bit stages and a 2-bit final stage. Bootstrapping switch is needed to provide the linearity in the front-end S/H. The 1.5b/stage architecture with digital error correction is used in this ADC for low-power and high-speed considerations. The input signal is fully differential; the input range is ±1 V. The ADC converter dissipates 146mW at a 50MHz clock rate with 3.3 V single supply voltage. Typical differential nonlinearity (DNL) is ±0.25LSB and integral nonlinearity (INL) is ±0.5LSB by MATLAB simulation.
|
|---|