Capacity Determination Model with Time Constraints and Batch Processing in Semiconductor Wafer Fabrication

• Main Authors: Chuen-Shiuan Liou, 劉醇玄
• Other Authors: Rong-Kwei Li
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/14449766467328012887

碩士 === 國立交通大學 === 管理學院碩士在職專班工業工程與管理組 === 94 === Recently, wafer fabrication has become more complicated and lengthened the produRct queue time. To ensure final product yield, engineers need to set up queue time limits for particular machines during wafer processing; we name it as “time constraints”. The problems of Time constraints are more serious when the time constraint are short, process are reentrant and batching. Generally, batch processing in wafer fabrication is matching these characteristics. To eradicate difficulties with time constraints and batching process, capacity planning must be addressed. This paper applied GI/G/m queuing theory to develop a capacity determination model for batch processing machines. The batching behavior is considered and taken as a factor to modify the mean and squared coefficient of variation of arrive rate in this model. Based on this queuing network model, the expected waiting time between machines in production systems can be estimated. Managers can also determine the capacity through the setting of expected rate of over time constraints. Furthermore, a checking table is derived for different utilizations, time constraints, and the probability of expected waiting time over time constraints. The approximate performance measures are compared with discrete-event simulation. The result presented the proposed model to be explored effectively and demonstrated a capability superior to the current planning method.