Design and Implementation of Front-End Integrated Circuit for Differential Capacitance Sensor
碩士 === 國立暨南國際大學 === 電機工程學系 === 94 === The major objective of this thesis is to design the differential capacitance sensing circuits which were used for many system applications. We choose the differential type of sensing circuit because this architecture could cancel the common mode level-shift effe...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28633944124387709806 |
| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 94 === The major objective of this thesis is to design the differential capacitance sensing circuits which were used for many system applications. We choose the differential type of sensing circuit because this architecture could cancel the common mode level-shift effect and stray capacitance in the circuit. This circuits include of two matching capacitance measuring circuit and a differential amplifier which transferred capacitance value to voltage value and read out the processed voltage signal. The proposed differential capacitance sensing circuit has been fabricated with TSMC 0.35um 2P4M CMOS technology. From the post-layout simulation showed that this circuit is operated at 0V~3.3V and its sensing range is 1fF~25fF under the baseline value of 10fF. The total output gain is 0.06V/1fF. Another experiment which was used HSPICE circuit simulation software showed the relation between sensing range and output gain under three different reference capacitors. When the large reference capacitor is used, it could display wide sensing range, but the output gain of the system will become smaller.
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