Characterization and Modeling of 0.18 μm nMOSFETs and its applications on the implementation of 3-5 GHz UWB LNA

• Main Authors: Meng-Hsiung Huang, 黃孟雄
• Other Authors: Yo-Sheng Lin
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/71348434907018132225

碩士 === 國立暨南國際大學 === 電機工程學系 === 94 === In the thesis, Modeling of 0.18 μm nMOSFETs is design and applications on the implementation of a 3-5 GHz UWB LNA. Research title have two parts： In first part, we can observe the S parameter, RF noise figure and power performance influenced by the several kinds of width and gate finger in RF MOSFETs. We analysis that the width is increasing and the kink effect point is conscious obviously, the lower frequency of kink effect point, the higher gate resistance (Rg) value, our results show the kink phenomena in S11 and S22. Then, after measure from NDL, we must use accurate de-embedding method to obtain intrinsic MOSFETs, because pad and transmission line will produce parasitic effect to influence on MOSFETs data which we want to take off. Previously, we use open de-embedding to extract S parameter of intrinsic MOSFETs, but S parameter will produce drift effect in high frequency after using open de-embedding method, because its method can not take off some intrinsic effect in high frequency. Hence, pass through improve three step de-embedding method, so we can obtain intrinsic MOSFETs and take off intrinsic effect clearly. Finally, we use S parameter of obtain intrinsic MOSFETs data to set up MOSFETs small-single models in TSMC 0.18 μm CMOS technology process which include intrinsic Bsim3v3 model for DC characteristics, series resistance of gate fingers, drain fingers and parasitic resistance between drain and silicon substrate. Furthermore, we can apply in the TSMC 0.35 μm technology process and set up its modeling, the construction of RF large-signal (and small-signal) model of TSMC 0.35 μm (and 0.18 μm) CMOS process. Based on the BSIM3v3 HSPICE model provided by TSMC, we construct scablable RF large-signal models of MOSFETs which can be applied up to 20 GHz. In second part, we demonstrate a miniaturized UWB low noise amplifier is implemented in 0.18 μm CMOS technology process for a 3–5 GHz UWB system. We use inductive-series peaking technique was used to enhance the gain and bandwidth performances of the LNA. The resistive shunt-shunt feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrow band LNA input and flattens the pass band gain. The measurement results show voltage gain greater than 20 dB, reverse isolation (S12) lower than 35 dB, and noise figure (NF) lower than 6 dB were achieved for frequencies lower than 5 GHz. In addition, input return loss (S11) lower than -9 dB was achieved for frequencies lower than 5 GHz. The chip area is only 0.66 mm2, excluding the test pads. This LNA drains 9.76 mA current at supply voltage of 2.5 V, i.e. it only consumes 24.4 mW power consumption. These results are helpful for RFIC designers to realize miniaturized receiver front-end ICs.