Real-Time MPEG-4 Codec System Based on SoC Realization

• Main Authors: Jo-Yuan Chen, 陳若元
• Other Authors: Jar-Ferr Yang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/19288355401856074797

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 94 === Real-Time MPEG-4 Codec System Based on SoC Realization Jo-Yuan Chen * and Jar-Ferr Yang** Institute of Computer and Communication Engineering, National Chen Kung University 1 University Road, Tainan, Taiwan, R.O.C. ABSTRACT In this thesis, we design a real-time MPEG-4 video codec system based on System-on-a-Chip - TMS320DM320 manufactured by Texas Instrument (TI) Incorporation. While implementing our system on DSP unit, we must consider solving the problems regarding to memory limitation, system parallelization and efficiency usage of fast instruction sets, etc. Firstly, we correct the major part of the codes or algorithms, and these operations on the program will be processed in efficient way by calling hardware acceleration module. Then, we translate the frequently-used C codes into assembly codes. Finally, according to the independency between hardware acceleration module and DSP system, we arrange system parallelization in order to accomplish a real-time MPEG-4 codec. Experiments show that our implementation can achieve real-time decoding and encoding in VGA and CIF format, respectively. In addition, take MPEG-4 decoder for example; we improve the efficiency of memory management by using overlay and dynamic linking loader technique without the influence of decoding performance. *The Author **The Advisor